Radiation-hardened phase-locked loop (PLL) circuits represent a critical advancement in safeguarding electronic systems against the deleterious effects of ionising radiation. These circuits are ...

Some brief theory and typical measurements of phase noise. Standard analysis of PLL phase noise used by most CAD applications. How to produce the lowest phase noise at a PLL output. A standard design ...

The clever trick comes by dividing the output frequency. For example, a 100 MHz crystal oscillator is difficult to design. But taking a voltage-controlled oscillator at 100 MHz (nominal) and dividing ...

One of the most challenging tasks in analog circuit design is to adapt a functional block to ever new CMOS process technology. For digital circuits the number of gates per square mm approx. doubles ...

The purpose of a phase locked loop (PLL) is to generate a frequency and phase-locked output oscillation signal. To achieve this goal, prior art essentially functioned ...

In this article, the phase noise of a closed-loop, phase-locked loop (PLL) synthesizer is simulated using Agilent RF Design Environment (RFDE) and Advanced Design System (ADS) tools. The critical ...

The NB4N507A is a fully integrated phase lock loop (PLL) designed to replace expensive crystal oscillators for clock generation in a variety of consumer and networking applications. The IC generates a ...

…which would take a pulse-width-modulated waveform at any frequency, and produce a signal with exactly the same mark/space ratio, but at a nominated frequency (see ‘Why might this be useful?’ below).