EDN

Demonstrating ASIC IP performance and quality demands an FPGA-neutral design flow

Companies designing new system-on-chip (SoC) products are subject to ongoing market pressure to do more with less and achieve higher returns. The result is shrinking engineering teams, reduced design ...
Design-Reuse

An FPGA primer for ASIC designers

With the advent of new technologies in IC design and complexity of the business models, chip designers may want to explore different choices available to them for implementation. ASICs have been the ...
Semiconductor Engineering

Synopsys FPGA Platform: Enabling Faster Design, Verification and Debug of FPGAs

FPGA development teams are adopting ASIC-style design, verification and debug methodologies. Here are the necessary elements of such a flow. September 11th, 2019 - By: Synopsys Field programmable gate ...
EDN

An FPGA primer for ASIC designers

With the advent of new technologies in IC design and complexity of the business models, chip designers may want to explore different choices available to them for implementation. ASICs have been the ...