EDN

VLSI papers weigh 65 nm, new circuits

AUSTIN, Texas — While technologists look to 65-nanometer nodes, circuit designers by and large are two generations back. So it's no surprise that as a string of 65-nm papers are delivered at the 2004 ...
Electronic Design

IEEE's Two-fer Deal: Two Virtual Symposia on VLSI Technology & Circuits for One Fee

Instead of being held in Waikiki, Hawaii, this year's IEEE joint symposium on VLSI Technology & Circuits will take place in cyberspace. Although the pandemic has put many aspects of our lives on hold, ...
IPWatchdog

Partial Win for VLSI Against Intel as CAFC Reverses PTAB on One Claim of Integrated Circuit Patent

“The CAFC agreed with VLSI’s construction, noting that the claims’ use of the phrase ‘being used for’ implies a requirement to use the metal interconnect layers to carry electricity.” In a ...
Semiconductor Engineering

Finite State Machine Synthesis In Programmable Circuits

Well, summer has been and gone; and for most of us it was a time to relax and reflect on our working practices. What can we do to achieve better results? And what can we do to break out of the routine ...
Semiconductor Engineering

LLM-Powered Automatic VLSI Design Flow Tuning Framework

A new technical paper titled “CROP: Circuit Retrieval and Optimization with Parameter Guidance using LLMs” was published by researchers at Duke University and Synopsys. “Modern very large-scale ...
TechRepublic

Low Power VLSI CMOS Design by DCG Technique

The demand for power-sensitive design has grown significantly in recent years due to tremendous growth in portable applications. Consequently, the need for power efficient design techniques has grown ...