Optics

Redefining Wafer-Level Packaging Production with Heidelberg Instruments Flexible Direct Writing Technology

Heidelberg, Germany – Heidelberg Instruments, a global player in direct write technology and solution provider for the advanced packaging market, is transforming the semiconductor industry with its ...
Digi Times

ACE’s wafer-level packaging to enter volume production in fourth quarter

Advanced Chip Engineering (ACE), engaged in development of wafer-level packaging technology, noted that its 6-inch products will enter mass production this October. Since last November, it has broken ...
Digi Times

Samsung steps up fan-out wafer-level packaging deployment

Samsung Electronics has stepped up its deployment in the fan-out (FO) wafer-level packaging segment with plans to set up related production lines in Japan, according to industry sources. Samsung has ...
Electronic Design

STMicroelectronics, STATS ChipPAC, And Infineon Join Forces On Wafer-Level-Packaging

Semiconductor makers STMicroelectronics and Infineon have teamed with 3D packaging provider STATS ChipPAC to jointly develop the next generation of embedded Wafer-Level Ball Grid Array (eWLB) ...
TweakTown

Apple iPhone 18 with A20 chip could switch to wafer-level multi-chip module packaging

TL;DR: Apple's iPhone 18 will feature the next-gen A20 chip using TSMC's advanced WMCM packaging with MUF technology, enhancing efficiency and yield. Eternal secured a major contract as a packaging ...
Fudzilla

TSMC gets fan-out (InFO) wafer-level packaging

All ready for 2016 TSMC is scheduled to move its integrated fan-out (InFO) wafer-level packaging technology to volume production in the second quarter of 2016. Apparently the fruity cargo cult… TSMC ...
Business Wire

Research and Markets: Global Wafer-level Packaging Equipment Market 2014-2018 with Applied Materials, Disco, EV Group, Tokyo Electron & Tokyo Seimitsu Dominating

DUBLIN--(BUSINESS WIRE)--Research and Markets (http://www.researchandmarkets.com/research/s9zs8w/global) has announced the addition of the "Global Wafer-level ...
Semiconductor Engineering

A Hybrid PLP Technology Based On A 650mm x 650mm Platform

A panel-level (PL) approach to fan-out (FO) packaging has been discussed for several years to reduce the cost of chip-first FO packaging based on redistribution layer (RDL) technology. More recently, ...
Seeking Alpha

NVE outlines accelerated growth plans with in-house wafer-level chip scale packaging and 4% sequential revenue increase

CEO Daniel Baker reported a 4% sequential increase in revenue for the quarter, highlighting strong increases in distributor and nondefense sales, despite an expected decrease in defense sales. Baker ...
Business Wire

SkyWater Florida and Deca Technologies Announce $120M DOD Award to Expand Advanced Packaging Capabilities in Osceola County, Florida

KISSIMMEE, Fla.--(BUSINESS WIRE)--SkyWater Technology (NASDAQ: SKYT), the trusted technology realization partner, and Deca Technologies (Deca), a leading provider of advanced electronic interconnect ...
Business Insider

ClassOne Technology Expands Solstice® Single-Wafer Portfolio with New 300mm Solstice Max Platform for Advanced Packaging Metallization

PHOENIX, Oct. 07, 2025 (GLOBE NEWSWIRE) -- SEMICON WEST -- ClassOne Technology, a leading global provider of advanced electroplating and wet processing tools for microelectronics manufacturing, today ...