Techniques that reduce the difficulty and cost associated with testing an integrated circuit. This can result in a decrease in the time spent on a tester, a decrease in cost associated with generating ...

The testing and verification of semiconductor chips was a prominent topic at this year’s European Test Systems (ETS) conference, especially in the area of Design-for-Test (DFT) tools and techniques.

Design-for-test (DFT) engineers often struggle to develop a memory built-in self-test (BIST) grouping plan, deciding which memories belong to which BIST group, to improve test time, routing effort, ...

The size of designs continues to grow and IC manufacturers are pushing for higher test quality, especially in mission-critical applications such as transportation and medicine. More advanced nodes ...